Welcome to the Etronic Hub,
The STM32F405xx and STM32F407xx series are built around the high-performance Arm® Cortex®-M4 32-bit RISC core, that runs up to 168 MHz. All Arm single-precision data-processing commands and data formats are supported by the Cortex-M4 core’s Floating point unit (FPU) single precision. It also includes a memory protection unit (MPU) and a full set of DSP commands to improve application security.
The STM32F405xx and STM32F407xx families have high-speed embedded memories (Flash memory up to 1 Mbyte, 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and a wide range of upgraded I/Os and peripherals connected to two APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.
Three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers, including two PWM timers for motor control, and two general-purpose 32-bit timers are all available on each device. a generator of true random numbers (RNG). There are additional ordinary and advanced communication interfaces available.
Board launch date: 2007
Board previous versions and after which version this was launched:
- In April 2010, ST announced the STM32 L1-series chips.
- In September 2010, ST announced the STM32VLDISCOVERY board.
- In November 2010, ST announced the STM32 F2-series chips based on the ARM Cortex-M3 core, and future development of chips based on the ARM Cortex-M4 and ARM Cortex-M3 cores.
Board previous version and this version comparison:
The F4-series is also the first STM32 series to have DSP and floating-point instructions. The F4 is pin-to-pin compatible with the STM32 F2-series and adds higher clock speed, 64 KB CCM static RAM, full-duplex I²S, improved real-time clock, and faster ADCs.
Board Working Temperature:
– 40 to +85 °C
- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Up to 1 Mbyte of Flash memory
- Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM
- 512 bytes of OTP memory
- Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
- LCD parallel interface, 8080/6800 modes
- Clock, reset and supply management
- 1.8 V to 3.6 V application supply and I/Os
- POR, PDR, PVD and BOR
- 4-to-26 MHz crystal oscillator
- Internal 16 MHz factory-trimmed RC (1% accuracy)
- 32 kHz oscillator for RTC with calibration
- Internal 32 kHz RC with calibration
- Low-power operation
- Sleep, Stop and Standby modes
- VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
- 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
- 2×12-bit D/A converters
- General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
- Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- Debug mode
- Serial wire debug (SWD) & JTAG interfaces
- Cortex-M4 Embedded Trace Macrocell™
- Up to 140 I/O ports with interrupt capability
- Up to 136 fast I/Os up to 84 MHz
- Up to 138 5 V-tolerant I/Os
- Up to 15 communication interfaces
- Up to 3 × I2C interfaces (SMBus/PMBus)
- Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
- Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
- 2 × CAN interfaces (2.0B Active)
- SDIO interface
- Advanced connectivity
- USB 2.0 full-speed device/host/OTG controller with on-chip PHY
- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
- 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
- 8- to 14-bit parallel camera interface up to 54 Mbytes/s
- True random number generator
- CRC calculation unit
- 96-bit unique ID
- RTC: subsecond accuracy, hardware calendar